Author Topic: 0x10c - Notch's New Game!  (Read 33570 times)

so how many of these things will be dropped and not put into the game?

Quote
Game Features
 

The game is still very early in development, but here is a list of things we hope to include:

• Hard science fiction.
• Lots of engineering.
• Fully working computer system.
• Space battles against the AI or other players.
• Abandoned ships full of loot.
• Duct tape!
• Seamlessly landing on planets.
• Advanced economy system.
• Random encounters.
• Mining, trading, and looting.
• Single and multi player connected via the multiverse.

so how many of these things will be dropped and not put into the game?


I hope as little as possible. Notch better not end this like Minecraft or I will lose all respect for him.


monthly fee. nope. no game is worth a monthly fee unless its like one penny.
honestly Tera is the only game i've ever bothered with a subscription for, and that's just for the easy Korean 8-year-old ass
(though i do get like a month free when it's out of beta so yay c:)

Notch will destroy us all with his virtual machines!

I'm a bit concerned at the number of registers included in his design.

I can't judge anything too seriously yet but I'm hoping they'll be some sort of mega register-file upgrade to like 30+ general purpose registers. The more, the better imo.

Notch hasn't explained the full restrictions on some of the registers either. It looks like A, B are directly accessed by the ALU while the rest are temporary memory locations ready to take input and output onto ports/things.

I'd like to see some proper documentation on the syntax but I'll wait D:

The scenario for the game made me crack a big smile. I've been more than once forgeted over by endianness and so have many of my students.

Later in the OP mentions single player with AI wouldn't be bound to the monthly fee. He's charging for simulating every single users worlds while they are offline. Although that idea sounds really, really stupid. We don't need our stuff to keep running while we are away, especially if we end up finding someone else destroyed our stuff while we were away.
Actually, yes, we DO want our stuff running while we're away. We could have auto pilot programs, or things to go mining for us while we're away. Of course I don't know what Notch has planned, but there is plenty that he could give us to accomplish while we're away.

Quote from: http://0x10c.com/doc/dcpu-16.txt
DCPU-16 Specification
Copyright 2012 Mojang
Version 1.1 (Check 0x10c.com for updated versions)

* 16 bit unsigned words
* 0x10000 words of ram
* 8 registers (A, B, C, X, Y, Z, I, J)
* program counter (PC)
* stack pointer (SP)
* overflow (O)

In this document, anything within [brackets] is shorthand for "the value of the RAM at the location of the value inside the brackets".
For example, SP means stack pointer, but [SP] means the value of the RAM at the location the stack pointer is pointing at.

Whenever the CPU needs to read a word, it reads [PC], then increases PC by one. Shorthand for this is [PC++].
In some cases, the CPU will modify a value before reading it, in this case the shorthand is [++PC].

Instructions are 1-3 words long and are fully defined by the first word.
In a basic instruction, the lower four bits of the first word of the instruction are the opcode,
and the remaining twelve bits are split into two six bit values, called a and b.
a is always handled by the processor before b, and is the lower six bits.
In bits (with the least significant being last), a basic instruction has the format: bbbbbbaaaaaaoooo



Values: (6 bits)
    0x00-0x07: register (A, B, C, X, Y, Z, I or J, in that order)
    0x08-0x0f: [register]
    0x10-0x17: [next word + register]
         0x18: POP / [SP++]
         0x19: PEEK / [SP]
         0x1a: PUSH / [--SP]
         0x1b: SP
         0x1c: PC
         0x1d: O
         0x1e: [next word]
         0x1f: next word (literal)
    0x20-0x3f: literal value 0x00-0x1f (literal)
   
* "next word" really means "[PC++]". These increase the word length of the instruction by 1.
* If any instruction tries to assign a literal value, the assignment fails silently. Other than that, the instruction behaves as normal.
* All values that read a word (0x10-0x17, 0x1e, and 0x1f) take 1 cycle to look up. The rest take 0 cycles.
* By using 0x18, 0x19, 0x1a as POP, PEEK and PUSH, there's a reverse stack starting at memory location 0xffff. Example: "SET PUSH, 10", "SET X, POP"



Basic opcodes: (4 bits)
    0x0: non-basic instruction - see below
    0x1: SET a, b - sets a to b
    0x2: ADD a, b - sets a to a+b, sets O to 0x0001 if there's an overflow, 0x0 otherwise
    0x3: SUB a, b - sets a to a-b, sets O to 0xffff if there's an underflow, 0x0 otherwise
    0x4: MUL a, b - sets a to a*b, sets O to ((a*b)>>16)&0xffff
    0x5: DIV a, b - sets a to a/b, sets O to ((a<<16)/b)&0xffff. if b==0, sets a and O to 0 instead.
    0x6: MOD a, b - sets a to a%b. if b==0, sets a to 0 instead.
    0x7: SHL a, b - sets a to a<<b, sets O to ((a<<b)>>16)&0xffff
    0x8: SHR a, b - sets a to a>>b, sets O to ((a<<16)>>b)&0xffff
    0x9: AND a, b - sets a to a&b
    0xa: BOR a, b - sets a to a|b
    0xb: XOR a, b - sets a to a^b
    0xc: IFE a, b - performs next instruction only if a==b
    0xd: IFN a, b - performs next instruction only if a!=b
    0xe: IFG a, b - performs next instruction only if a>b
    0xf: IFB a, b - performs next instruction only if (a&b)!=0
   
* SET, AND, BOR and XOR take 1 cycle, plus the cost of a and b
* ADD, SUB, MUL, SHR, and SHL take 2 cycles, plus the cost of a and b
* DIV and MOD take 3 cycles, plus the cost of a and b
* IFE, IFN, IFG, IFB take 2 cycles, plus the cost of a and b, plus 1 if the test fails
   

   
Non-basic opcodes always have their lower four bits unset, have one value and a six bit opcode.
In binary, they have the format: aaaaaaoooooo0000
The value (a) is in the same six bit format as defined earlier.

Non-basic opcodes: (6 bits)
         0x00: reserved for future expansion
         0x01: JSR a - pushes the address of the next instruction to the stack, then sets PC to a
    0x02-0x3f: reserved
   
* JSR takes 2 cycles, plus the cost of a.



FAQ:

Q: Why is there no JMP or RET?
A: They're not needed! "SET PC, <target>" is a one-instruction JMP.
   For small relative jumps in a single word, you can even do "ADD PC, <dist>" or "SUB PC, <dist>".
   For RET, simply do "SET PC, POP"
   
Q: How does the overflow (O) work?
A: O is set by certain instructions (see above), but never automatically read. You can use its value in instructions, however.
   For example, to do a 32 bit add of 0x12345678 and 0xaabbccdd, do this:
      SET [0x1000], 0x5678    ; low word
      SET [0x1001], 0x1234    ; high word
      ADD [0x1000], 0xccdd    ; add low words, sets O to either 0 or 1 (in this case 1)
      ADD [0x1001], O         ; add O to the high word
      ADD [0x1001], 0xaabb    ; add high words, sets O again (to 0, as 0xaabb+0x1235 is lower than 0x10000)

Q: How do I do 32 or 64 bit division using O?
A: This is left as an exercise for the reader.
     
Q: How about a quick example?
A: Sure! Here's some sample assembler, and a memory dump of the compiled code:

        ; Try some basic stuff
                      SET A, 0x30              ; 7c01 0030
                      SET [0x1000], 0x20       ; 7de1 1000 0020
                      SUB A, [0x1000]          ; 7803 1000
                      IFN A, 0x10              ; c00d
                         SET PC, crash         ; 7dc1 001a

                     
        ; Do a loopy thing
                      SET I, 10                ; a861
                      SET A, 0x2000            ; 7c01 2000
        :loop         SET [0x2000+I], [A]      ; 2161 2000
                      SUB I, 1                 ; 8463
                      IFN I, 0                 ; 806d
                         SET PC, loop          ; 7dc1 000d

       
        ; Call a subroutine
                      SET X, 0x4               ; 9031
                      JSR testsub              ; 7c10 0018

                      SET PC, crash            ; 7dc1 001a

       
        :testsub      SHL X, 4                 ; 9037
                      SET PC, POP              ; 61c1
                       
        ; Hang forever. X should now be 0x40 if everything went right.
        :crash        SET PC, crash            ; 7dc1 001a

       
        ;
  • : Note that these can be one word shorter and one cycle faster by using the short form (0x00-0x1f) of literals,

        ;      but my assembler doesn't support short form labels yet.     

  Full memory dump:
 
        0000: 7c01 0030 7de1 1000 0020 7803 1000 c00d
        0008: 7dc1 001a a861 7c01 2000 2161 2000 8463
        0010: 806d 7dc1 000d 9031 7c10 0018 7dc1 001a
        0018: 9037 61c1 7dc1 001a 0000 0000 0000 0000
CPU specs are now at, time to brush up on assembly!

I don't like the very low cycle times on some of those instructions.

It's been awhile since I've done assembly, aren't low cycle times good?

Yes but 3 cycles for a division instruction seems abnormally low. Division is an expensive operation and a lot of stuff I've seen has arithmetic division instructions taking 20+ cycles.

Also, LOL at the monthly fee. You hear people talking about how notch is a greedy forget, but now I see that's pretty much true.

i love fees. keeps the bulk of the stuffty children out

i love fees. keeps the bulk of the stuffty children out

But then causes the spoiled bitch children to gain more ground.


ALSO Notch has millions made from Minecraft. he doesnt need a montly fee from people.


ALSO ALSO I had an idea for a game like this, so i hope Notch doesnt screw it up

I hope it isn't as bad as Minecraft and Cobalt. The monthly fee shouldn't be there, just charge less in the early stages.
Not only is cobalt not made by Mojang there is nothing wrong with it and is also quite fun.

But then causes the spoiled bitch children to gain more ground.

that dosnt even make any sense. you sound like one of those stuffty children i was talking about.